The present invention is related to hardware used to support the polling of devices on a bus.
Reducing power consumption by computer systems has become of increasing importance in recent years to satisfy increasing demands of users to reduce operating costs or to provide longer operating times in the case of portable computer systems. However, the goal of reducing power consumption has come into ever greater conflict with the goal of providing increasingly more flexible support for an ever greater array of I/O devices as more and more measures have been taken to reduce power consumption by xe2x80x9cpowering downxe2x80x9d more and more of the components that comprise a typical computer system.
Numerous measures have been taken to power down ever more of the circuitry comprising a computer system whenever various degrees of inactivity seem to provide opportunities to do so. However, where it is intended that a computer system is to remain responsive enough to a user or other stimuli such that components that have been powered down are able to be powered up again when needed, a need remains to have at least some portion of the circuitry remain active to enable such a response.
One measure to reduce power entails powering down at least a portion of the processor used in a computer system, especially where the processor is likely to consume a large proportion of the power consumed by the whole computer system. In support of allowing the processor to power down and remain powered down for longer periods of time, one or more I/O devices may be configured to operate under the control of controlling circuitry capable of operating independently of the processor to perform one or more minor tasks in support of the I/O devices.
Some of such minor tasks in support of I/O devices require the controlling circuitry to make accesses to memory shared between the controlling circuitry and the processor. Controlling circuitry capable of making such accesses to such memory are often referred to as xe2x80x9cbus masters,xe2x80x9d because making such an access to such memory usually requires gaining control of a memory bus that both the processor and the bus master share to obtain such access.
In some computer systems, the support of one or more I/O devices requires the repetitive polling of I/O devices to obtain status at frequent intervals by such an I/O bus master. This polling may further require repetitive accesses by the I/O bus master to the memory, and this prevents the memory from being powered down at times when it otherwise could be. Also, where a computer system also includes a cache maintained by the processor, such repetitive accesses by the I/O bus master to the memory may also prevent the processor from being powered down when it otherwise could be so that the processor may perform operations required to maintain cache coherency with the contents of the memory in response to the I/O bus master""s accesses.
A need exists to reduce the frequency of accesses by such an I/O bus master in support of polling I/O devices.